Some integrated circuit (IC) packages, such as ball grid array (BOA) packages may include a substrate that can be similar to a very small printed-circuit board (PCB). Such a substrate may typically include a number of layers that are laminated together. For example, the substrate can be used to route signals from the “die” or “chip,” or multiple chips, to the balls on the bottom of the BGA package for connection to the outside world (e.g., via a larger PCB). A conventional BGA package is shown in FIG. 1 and indicated by the general reference character 100. Die or chip 102 can have a number of bonding pads (not shown) for connection via bond wires 110. Substrate 104 can include substrate traces 108 for electrical connections from bond wires 110 to balls 106. Substrate traces 108 can reside in one or more routing layers of substrate 104.
The cost of a BGA substrate (e.g., substrate 104) may be directly correlated to the number of layers (e.g., for making or insulating substrate traces 108) used in the substrate. In such a BGA substrate, bond pads on an IC may be connected via substrate traces to the BGA balls, as shown. However, a substrate design or arrangement of substrate traces (e.g., 108) in relation to external connections (e.g., balls 106) and bond pad connectors (e.g., bond wires 110) can sometimes be difficult. For example, it may be difficult to route some traces 108 without crossing or overlapping another trace 108 or a ball 106.
Among the factors or design considerations adding to this difficulty are the number of connections to be made, the size of the BGA substrate, the BGA ball assignment and geometric pattern, and the IC signal assignment or bond pad locations on the chip. For example, it may be necessary at times to electrically connect a bond pad on one side of the die 102 to a ball 106 at a remote location (e.g., an opposite side) of the substrate 104. Often, it may be necessary to increase the number of layers in the BGA or other such package substrate in order to successfully route the IC signals (e.g., from the bond pads on the chip) to the BGA balls (e.g., 106), and this generally adds expense to the BGA package.
Accordingly, one drawback of conventional approaches for BGA or other IC package substrates is the additional cost associated with adding more layers to complete routing via the substrate traces. As such, a substrate having fewer layers may generally be less expensive than a comparable substrate with a relatively large number of layers. Thus, it would be desirable to have a method and apparatus that reduces or minimizes the number of layers used in an IC package substrate.